NAND flash-based storage devices have been widely adopted because of their faster read/write performance, lower power consumption, and shock proof features. One drawback is their relatively higher price as compared to hard disk drives (HDD). In order to bring costs down, NAND flash manufacturers have been pushing the limits of their fabrication processes towards 20 nm and lower, which often leads to a shorter usable lifespan and a decrease in data reliability. As such, a much more powerful error correction code (ECC) is required over traditional BCH codes to overcome the associated noises and the interferences, and therefore improve the data integrity. One such ECC is low-density parity-check (LDPC) code. However, handling LDPC codes requires often requires a large amount of computing and associated power resources. Therefore there exists a need for a high speed and power efficient way to handle LDPC codes.